The larger fan-in of the 6-input LUT means fewer levels of logic may be traversed by the critical path within each cluster, potentially reducing the total contribution of intra-cluster delay to the critical path. The total logic capability of the cluster (that is, the amount of user logic that the cluster can accommodate) is similar in each case. The PolarFire SONOS configuration cell is immune to SEUs.Ĭonsider a PolarFire FPGA cluster of twelve 4-input LUTs versus a cluster of eight 6-input LUTs. This traditional observation applies even more strongly to advanced fabrication technologies because SRAM configuration memory has not scaled as fast as ordinary logic, due to the need to mitigate the risk of SEUs. One contributing factor is that a 6-input LUT requires 4x more configuration memory bits (64 versus 16) but can accommodate only about 1.6x as much logic as a 4-input LUT. A given user design can be implemented with less silicon area using a 4-LUT architecture than using a 6-LUT architecture. It has been well-established that 4-input LUTs can make more efficient use of a die area than 6-input LUTs. Some attributes of the PolarFire’s FPGAs (such as the non-volatile configuration memory) directly reduce power, while power reduction in an indirect effect of reducing die area in other cases.Ħ-input LUTs can provide some speed benefits, but 4-input LUTs are the better choice for a power and cost-optimized FPGA like Microsemi’s in a modern process technology. Microsemi’s PolarFire FPGAs typically consume one-tenth the static power of competing SRAM FPGAs, and half the total power. In designing the FPGA programmable logic fabric, we aimed to meet mainstream performance requirements with minimal power and cost.
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